Altera QDRII SRAM Controller MegaCore Function - Manual (Page 52)

3–20 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
Interfaces & Signals
Figure 3–17. Simultaneous Read & Write—Burst of Four (Narrow Mode)
Burst of Two
For the burst of two, the protocol already allows simultaneous reads and
writes by asserting readn and writen and their respective addresses for
only half a clock cycle. No arbitration on the Avalon interface is required
and you can use the full bandwidth, without even losing any initial
cycles.
Figure 3–18 on page 3–21 shows concurrent reads and writes in a
burst of two configuration.
1000 1001 1002 1003
0102 0304 0506 0708 0708
3000 3001 3002 3003
1112 1314 1516 1718 1718
3000 1000 3002 1002
11 12 13 14 15 16 17 18 18
01 02 03 04 05 06 07 08 08
avl_clk
avl_read
avl_adr_rd[19:0]
avl_wait_request_rd
avl_data_read_valid
avl_data_rd[17:0]
avl_write
avl_adr_wr[19:0]
avl_wait_request_wr
avl_data_wr[17:0]
qdrii_k
qdrii_a[19:0]
qdrii_d[17:0]
qdrii_wpsn
qdrii_rpsn
qdrii_cqn
qdrii_cq
qdrii_q[17:0]