Altera QDRII SRAM Controller MegaCore Function - Manual (Page 20)

2–10 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
QDRII SRAM Controller Walkthrough
2. After you review the generation report, click Exit to close IP
Toolbench.
You have finished the walkthrough. Now, simulate the example design
(refer to
“Simulate the Example Design” on page 2–11 ), edit the PLL(s)
(refer to “Edit the PLL” on page 2–18 ), and compile (refer to “Compile the
Example Design” on page 2–19 ).
name>_auk_qdrii_sram_pipe_resynch_wrapper.v
hd or .v File that includes the write data pipeline and includes the
address and command, read command, write data, and
write command pipeline.
name>_auk_qdrii_sram_pipeline_addr_cmd.vhd
or .v Address and command pipeline.
name>_auk_qdrii_sram_pipeline_rdata.vhd or .v Read data pipeline.
name>_auk_qdrii_sram_pipeline_wdata.vhd or .v Write data pipeline.
name>_auk_qdrii_sram_read_group.vhd or .v The read registers.
name>_auk_qdrii_sram_resynch_reg.vhd or .v The resynchronization FIFO buffers.
name>_auk_qdrii_sram_train_wrapper.vhd or .v File that contains all the training group modules.
name>_auk_qdrii_sram_test_group.vhd or .v Training module, which realigns latency.
name>_auk_qdrii_sram_write_group.vhd or .v The write registers.
<variation name>.qip Contains Quartus II project information for your
MegaCore function variations.
.vhd or .v (1) Example design file.
add_constraints_for_.tcl The add constraints script.
qdrii_pll_stratixii.vhd or .v Stratix II PLL.
Notes to Table 2–1 :
(1) <top-level name> is the name of the Quartus II project top-level entity.
(2) <variation name> is the name you give to the controller you create with the Megawizard.
(3) IP Tooblench replaces the string qdrii_sram with qdriiplus_sram for QDRII+ SRAM controllers.
Table 2–1. Generated Files (Part 2 of 2) (1) , (2) & (3)
Filename Description