Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 53)

Figure 5-3: Mixed-Port Read-During-Write
This figure shows the timing diagram of when the mixed-port read-during-write occurs.
At 12500 ps, mixed-port read-during-write occurs when data
cc
is both written to port A, and is reading
from port B, simultaneously targeting the same address 1. Because the true dual-port RAM that is
configured to mixed-port read-during-write is showing the old data, the
rdata2
port shows the old data
bb
after four clock cycles at 27500 ps. When the data is read again from the same address at the next rising
clock edge at 17500 ps, the
rdata2
port shows the recent data cc at 32500 ps.
UG-01068
2014.12.17
Simulation Results 5-7
Design Example Altera Corporation
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