Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 15)

Mixed-width Port Configuration
Only dual-port RAM and dual-port ROM support mixed-width port configuration for all memory block
types except when they are implemented with LEs. The support for mixed-width port depends on the
width ratio between port A and port B. In addition, the supporting ratio varies for various memory
modes, memory blocks, and target devices.
Note: MLABs do not have native support for mixed-width operation, thus the option to select MLABs is
disabled in the parameter editor. However, the Quartus II software can implement mixed-width
memories in MLABs by using more than one MLAB. Therefore, if you select AUTO for your
memory block type, it is possible to implement mixed-width port memory using multiple MLABs.
Memory depth of 1 word is not supported in simple dual-port and true dual-port RAMs with mixed-
width port. The parameter editor prompts an error message when the memory depth is less than 2 words.
For example, if the width for port A is 4 bits and the width for port B is 8 bits, the smallest depth
supported by the RAM is 4 words. This configuration results in memory size of 16 bits (4 × 4) and can be
represented by memory depth of 2 words for port B. If you set the memory depth to 2 words that results
in memory size of 8 bits (2 × 4), it can only be represented by memory depth of 1 word for port B, and
therefore the width of the port is not supported.
Maximum Block Depth Configuration
You can limit the maximum block depth of the dedicated memory block you use.
The memory block can be sliced to your desired maximum block depth. For example, the capacity of an
M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1
bit (8K × 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and
each address is capable of storing up to 18 bits (512 × 18).
You can use this option to save power usage in your devices. However, this parameter might increase the
number of LEs and affects the design performance.
When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a
depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower
slices.
You can also use this option to reduce the total number of memory blocks used (but at the expense of
LEs). The 8K × 36 RAM uses 36 M9K RAM blocks with a default slicing of 8K × 1. By setting the
maximum block depth to 1K, the 8K × 36 RAM can fit into 32 M9K blocks.
The maximum block depth must be in a power of two, and the valid values vary among different
dedicated memory blocks.
Table 3-3: Valid Range of Maximum Block Depth for Various Embedded Memory Blocks
Embedded Memory Blocks Valid Range (6)
M10K 256–8K
M20K 512–16K
(6) The maximum block depth must be in a power of two.
UG-01068
2014.12.17
Mixed-width Port Configuration 3-5
Embedded Memory Functional Description Altera Corporation
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