Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 25)

Error Correction Code
Error correction code (ECC) allows you to detect and correct data errors at the output of the memory.
The Stratix III and Stratix IV M144K memory blocks have built-in ECC support of up to x64-wide simple
dual-port mode while the Stratix V M20K memory blocks have built-in ECC support of x32-wide simple
dual-port mode. The ECC in Stratix III and IV can perform single-error-correction double-error
detection (SECDED), in which it can detect and fix a single-bit error or detect two-bit errors (without
fixing). The Stratix V ECC feature can perform single error correction, double adjacent error correction,
and triple adjacent error detection, in which it can detect and fix a single bit error event or a double
adjacent error event, or detect three adjacent errors without fixing the errors. However, the Stratix V ECC
feature cannot detect four or more errors.
The ECC feature is not supported in the following conditions:
• mixed-width port feature is used
• byte-enable feature is engaged
Note: The Mixed-port RDW for old data mode is not supported when the ECC feature is engaged. The
result for RDW is Don't Care.
The M144K ECC status is communicated via a three-bit status flag eccstatus[2..0]. while the M20K ECC
status is communicated with a two-bit ECC status flag eccstatus[1..0] where eccstatus[1] corresponds to
the signal e (error) and eccstatus[0] corresponds to the signal ue (uncorrectable error).
Status
M144K M20K
eccstatus[2..0]
eccstatus[1..0]
eccstatus[1] e eccstatus[0] ue
No error 000 0 0
Single error and fixed 011 — —
Double error and no fix 101 — —
Illegal
001 0 1
010 0 1
Illegal
100 0 1
11X 0 1
A correctable error occurred
and the error has been
corrected at the outputs;
however, the memory array
has not been updated.
— 1 0
An uncorrectable error
occurred and uncorrectable
data appears at the output.
— 1 1
UG-01068
2014.12.17
Error Correction Code 3-15
Embedded Memory Functional Description Altera Corporation
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