Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 45)

Parameter Legal Values Description
What clocking method would you like to use?
• Single clock
• Dual clock: use
separate ‘input’
and ‘output’
clocks
• Dual clock: use
separate clocks
for A and B ports
Specifies the clocking
method to use.
• Single clock—A single
clock and a clock enable
controls all registers of
the memory block
• Dual clock: use separate
‘input’ and ‘output’
clocks—The input clock
controls the address
registers and the output
clock controls the data-
out registers. There are no
write-enable, byte-enable,
or data-in registers in
ROM mode.
• Dual clock: use separate
clocks for A and B ports
—Clock A controls all
registers on the port A
side; clock B controls all
registers on the port B
side. Each port also
supports independent
clock enables for both
port A and port B
registers, respectively.
Create a ‘rden_a’ and ‘rden_b’ read enable signals — Specifies whether to create
read enable signals.
Parameter Settings: Regs/Clkens/Aclrs
Read output port(s) ‘q_a’ and ‘q_b’
On/Off Specifies whether to register
the ‘q_a’ and ‘q_b’ output
ports.
More Options
‘q_a’ port On/Off Specifies whether to register
the ‘q_a’ output port.
‘q_b’ port On/Off Specifies whether to register
the ‘q_b’ output port.
Create one clock enable signal for each clock signal. On/Off Specifies whether to turn on
the option to create one
clock enable signal for each
clock signal.
4-20 ROM: 2-PORT IP Core Parameters
UG-01068
2014.12.17
Altera Corporation Embedded Memory Signals and Parameters
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