Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 39)

Parameter Legal Values Description
More Options
When you select
With one read port
and one write port,
the following options
are available:
• Create an ‘wr_
addressstall’ input
port.
• Create an ‘rd_
addressstall’ input
port.
When you select
With two read /
write ports, the
following options are
available:
• Create an
‘addressstall_a’
input port.
• Create an
‘addressstall_b’
input port.
On/Off Specifies whether to create
clock enables for address
registers. You can create
these ports to act as an extra
active low clock enable input
for the address registers.
Create an ‘aclr’ asynchronous clear for the
registered ports.
On/Off Specifies whether to create
an asynchronous clear port
for the registered ports.
More Options
When you select
With one read port
and one write port,
the following options
are available:
• ‘q_b’ port
• ‘rdaddress’ port
When you select
With two read /write
ports, the following
options are available:
• ‘q_a’ port
• ‘q_b’ port
On/Off Specifies whether the
‘raddress’, ‘q_a’, and ‘q_b’
ports are cleared by the aclr
port.
Parameter Settings: Output 1
4-14 RAM: 2-Port IP Core Parameters
UG-01068
2014.12.17
Altera Corporation Embedded Memory Signals and Parameters
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