Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 27)

Signal Type Required Description
byteena_a
Input Optional Byte enable input to mask the
data_a
port so that only
specific bytes, nibbles, or bits of the data are written.
The
byteena_a
port is not supported in the following
conditions:
• If
implement_in_les
parameter is set to ON
• If
operation_mode
parameter is set to ROM
addressstall_a
Input Optional Address clock enable input to hold the previous address of
address_a port for as long as the addressstall_a port is
high.
q_a
Output Yes Data output from port A of the memory.
The
q_a
port is required if the
operation_mode
parameter
is set to any of the following values:
•
SINGLE_PORT
•
BIDIR_DUAL_PORT
•
ROM
The width of
q_a
port must be equal to the width of
data_
a
port.
data_b
Input Optional Data input to port B of the memory.
The
data_b
port is required if the
operation_mode
parameter is set to
BIDIR_DUAL_PORT
.
address_b
Input Optional Address input to port B of the memory.
The
address_b
port is required if the
operation_mode
parameter is set to the following values:
•
DUAL_PORT
•
BIDIR_DUAL_PORT
wren_b
Input Yes Write enable input for
address_b
port.
The
wren_b
port is required if
operation_mode
is set to
BIDIR_DUAL_PORT
.
rden_b
Input Optional Read enable input for
address_b
port. The
rden_b
port is
supported depending on your selected memory mode and
memory block
byteena_b
Input Optional Byte enable input to mask the
data_b
port so that only
specific bytes, nibbles, or bits of the data are written.
The
byteena_b
port is not supported in the following
conditions:
• If
implement_in_les parameter
is set to
ON
• If
operation_mode parameter
is set to
SINGLE_PORT
,
DUAL_PORT
, or
ROM
4-2 Signals
UG-01068
2014.12.17
Altera Corporation Embedded Memory Signals and Parameters
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