Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 31)

Signal Type Required Description
aclr
Input Optional Asynchronously clear the registered input and output
ports. The asynchronous clear effect on the registered
ports can be controlled through their corresponding
asynchronous clear parameter, such as
indata_aclr
,
wraddress_aclr
, and so on.
RAM:1-Port IP Core Parameters
This table lists the parameters for the RAM:1-Port IP Core
Table 4-2: RAM: 1-Port IP Core Parameters
Parameter Legal Values Description
Parameter Settings: Widths/Blk Type/Clks
How wide should the ‘q’ output bus be?
— Specifies the width of the ‘q’
output bus.
How many -bit words of memory? — Specifies the number of -bit
words.
What should the memory block type be? Auto, M-RAM, M4K,
M512, M9K, M10K,
M144K, MLAB, M20K,
LCs
Specifies the memory block
type. The types of memory
block that are available for
selection depends on your target
device.
Set the maximum block depth to Auto, 32, 64, 128, 256, 512,
1024, 2048, 4096,
8192,16384, 32768, 65536
Specifies the maximum block
depth in words.
What clocking method would you like to
use?
• Single clock
• Dual clock: use separate
‘input’ and ‘output’
clocks
Specifies the clocking method to
use.
• Single clock—A single clock
and a clock enable controls
all registers of the memory
block.
• Dual clock: use separate
‘input’ and ‘output’ clocks
—An input and an output
clock controls all registers
related to the data input and
output to/from the memory
block including data,
address, byte enables, read
enables, and write enables.
Parameter Settings: Regs/Clken/Byte Enable/Aclrs
4-6 RAM:1-Port IP Core Parameters
UG-01068
2014.12.17
Altera Corporation Embedded Memory Signals and Parameters
Send Feedback