Design example, Design example -1 – Altera Internal Memory (RAM and ROM) IP Core User Manual
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Design Example
5
2014.12.17
UG-01068
Simulate the designs using the ModelSim
®
-Altera software to generate a waveform display of the device
behavior.
The following design files in
Internal_Memory_DesignExample.zip
:
• ecc_encoder.v
• ecc_decoder.v
• true_dp_ram.v
• top_dpram.v
• true_dp_ram.vt
• true_dp.do
• true_dp.qar (Quartus II design file)
Related Information
•
Provides the design examples for this user guide
•
The support page includes links to such topics as installation, usage, and troubleshooting for the
ModelSim-Altera software
External ECC Implementation with True-Dual-Port RAM
The ECC features are only supported internally in simple dual-port RAM by Stratix IV devices when the
M144K is implemented or by Stratix V when the M20K is implemented. Therefore, this design example
describes how ECC features can be implemented in other RAM modes, regardless of the type of device
memory block you use. It also demonstrates the features of the same-port and mixed-port read-during-
write behaviors.
This design example uses a true dual-port RAM and illustrates how the ECC feature can be implemented
external to the RAM. The ALTECC_ENCODER and ALTECC_DECODER IP cores are required as the
ALTECC_ENCODER IP core encodes the data input before writing the data into the RAM, while the
ALTECC_DECODER IP core decodes the data output from the RAM before transferring the data out to
other parts of the logic.
In this design example, the raw data width is 8 bits and is encoded by the ALTECC_ENCODER IP core
block to produce a 13-bit width data that is written into the true dual-port RAM when write-enable signal
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