Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 2)

Contents
About RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT
IP Cores............................................................................................................1-1
Embedded Memory Features..................................................................................................................... 1-1
Supported Memory Operation Modes......................................................................................................1-2
Customizing Embedded Memory IP Cores........................................................ 2-1
Installing and Licensing IP Cores..............................................................................................................2-1
IP Catalog and Parameter Editor...............................................................................................................2-2
Using the Parameter Editor........................................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Migrating IP Cores to a Different Device.................................................................................................2-4
Embedded Memory Functional Description...................................................... 3-1
Memory Block Types...................................................................................................................................3-1
Write and Read Operations Triggering.................................................................................................... 3-2
Port Width Configurations.........................................................................................................................3-4
Mixed-width Port Configuration...............................................................................................................3-5
Maximum Block Depth Configuration.....................................................................................................3-5
Clocking Modes and Clock Enable............................................................................................................3-6
Memory Blocks Address Clock Enable Support......................................................................................3-7
Byte Enable ...................................................................................................................................................3-8
Asynchronous Clear.................................................................................................................................. 3-10
Read Enable................................................................................................................................................ 3-10
Read-During-Write................................................................................................................................... 3-11
Selecting RDW Output Choices for Various Memory Blocks.................................................3-12
Power-Up Conditions and Memory Initialization................................................................................3-14
Error Correction Code .............................................................................................................................3-15
Embedded Memory Signals and Parameters......................................................4-1
Signals............................................................................................................................................................4-1
RAM:1-Port IP Core Parameters...............................................................................................................4-6
RAM: 2-Port IP Core Parameters..............................................................................................................4-9
ROM: 1-PORT IP Core Parameters........................................................................................................4-16
ROM: 2-PORT IP Core Parameters........................................................................................................4-18
Design Example................................................................................................... 5-1
External ECC Implementation with True-Dual-Port RAM.................................................................. 5-1
Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-
PORT IP Core.............................................................................................................................5-2
TOC-2
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