Altera SoC Embedded Design Suite - Manual (Page 112)

Figure 4-66: Edit DTSL Options Button
5. In the DTSL windowDTSL dialog box, click Trace Buffer tab and select On Chip Trace Buffer (ETF)
for the Trace capture method.
Figure 4-67: Trace Into ETF
6. In the DTSL dialog box, click the Cortex-A9 tab, and enable tracing for both cores.
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Getting Started with Tracing 4-93
Getting Started Guides Altera Corporation
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