Common parameters – Altera PHYLite User Manual
Page 46

Figure 21: ALTDQ_DQS2 IP Core Parameter for Stratix V Devices
Common Parameters
Table 23: Common Parameters
This table lists the common parameters for the Altera PHYLite for Parallel Interfaces and ALTDQ_DQS2 IP
cores.
ALTDQ_DQS2 IP core
Altera PHYLite for Parallel Interfaces IP core
Pin Width
Pin Width
Pin Type
Pin Type
Memory frequency
Memory clock frequency
Use dynamic configuration scan chains
Use dynamic reconfiguration
Use half-rate output path.
Note: Supports only full or half-rate.
Clock rate of user logic
Note: Supports only full, half, or quarter-rate.
Capture strobe type
Note: Supports single, complementary, and
differential strobes.
Strobe configuration
Note: Supports single ended, complementary,
and differential strobes.
DQS phase shift
Capture strobe phase shift
Generate Output strobe
Use Output strobe
46
Common Parameters
ug_altera_phylite
2015.01.16
Altera Corporation
Altera PHYLite for Parallel Interfaces IP Core User Guide
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
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