Calibrated vref settings, Input buffer, Vref calibration block – Altera PHYLite User Manual
Page 13: Resistor ladder
Figure 13: VREF
Input Buffer
+
-
Vref
R
R
VCCN
Internal VREF
6 bits binary weighted resistors dividor
6 bits Static VREF Code
6 bits calibrated VREF code from Avalon bus
VREF Calibration Block
+
-
VCCN
Rt
External VREF
Resistor
Ladder
Calibrated VREF Settings
Table 7: Calibrated VREF Settings
This table lists the calibrated VREF settings that you can set over the Avalon calibration bus.
avl_writedata[5:0]
% of VCCN
000000
60.00%
000001
60.64%
000010
61.28%
000011
61.92%
000100
62.56%
ug_altera_phylite
2015.01.16
Calibrated VREF Settings
13
Altera PHYLite for Parallel Interfaces IP Core User Guide
Altera Corporation
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