Altera PHYLite - Manual (Page 26)

Figure 15: Lane and Pin Placement Dependent Addresses
This figure shows an example of a placed group with two lanes, 16 data pins and a differential strobe.
In order to provide a unified way to look up reconfigurable feature addresses for a specific interface both
before and after placement, the address information is stored in memory in the I/O column. This memory
is addressable over the same Avalon-MM bus as is used for feature reconfiguration.
Table 13: Memory Look Up Components
This table lists the two main components to the memory look-up.
Component Description
Global parameter table Stores pointers to the individual interface parameter tables. The
global parameter table lists all interfaces in the column (both
the Arria 10 External Memory Interfaces and Altera PHYLite
for Parallel Interfaces IP cores).
Set of individual interface parameter
tables
Contain interface specific information. This is where pin and
lane level address look-ups are performed.
26 Address Look-Up
ug_altera_phylite
2015.01.16
Altera Corporation Altera PHYLite for Parallel Interfaces IP Core User Guide
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