Timing closure guidelines, Timing closure: dynamic reconfiguration, Timing closure: non edge-aligned input data – Altera PHYLite User Manual
Page 19: I/o timing violation
Location
Description
FPGA
The Altera PHYLite for Parallel Interfaces IP core generation creates the clock settings for the
user core clock and the periphery clock in the following formats:
• user core clock—
• periphery clock—
The user core clock is for user core logic and the periphery clock is the clock for the PHYLite
periphery hardware. With these clock settings, the TimeQuest Timing Analyzer analyzes the
timing of the Altera PHYLite for Parallel Interfaces IP core interface transfer and within core
transfer correctly.
Timing Closure Guidelines
Timing Closure: Dynamic Reconfiguration
You can dynamically reconfigure the delay elements in the I/O to optimize process, voltage, temperature
variations by implementing a calibration algorithm that modifies the input and output delays (refer to
on page 20).
The SDC cuts the I/O transfer paths and you must verify the reconfiguration algorithm to ensure that
your I/O transfers are working. The Quartus II software issues the following critical warning:
Dynamic Reconfiguration is ON but user has not set var(dynamic_reconfigura-
tion_algorithm_verified) to 1. Please set to 1 after calibration algorithm is
extensively verified. I/O timing analysis may not represent the system.
After verifying the algorithm, you can disable the critical warning by editing the .sdc file and set the
following variable to
1
:
var(dynamic_reconfiguration_algorithm_verified)
Timing Closure: Non Edge-Aligned Input Data
If the input data is not edge-aligned, modify the timing settings of the group to match the system. Convert
input strobe phase shift to nanosecond and subtract it from Input Strobe Setup Delay Constrain and
Input Strobe Hold Delay Constrain parameters.
If the input data is center-aligned with the input strobe, subtract the 90° phase shift from the Input Strobe
Setup Delay Constrain and Input Strobe Hold Delay Constrain parameters in the
Setup Delay Constrain parameter is 0.1, change the value to 0.1-1.25*(90/360) = -0.2125.
Note: Ensure that you make the changes in the Input Strobe Setup Delay Constrain and Input Strobe
Hold Delay Constrain parameters.
I/O Timing Violation
At high frequency configuration, it is difficult to achieve timing closure at I/O. Consider using the Arria
10 External Memory Interface IP core or the dynamic reconfiguration feature to calibrate the I/O path.
ug_altera_phylite
2015.01.16
Timing Closure Guidelines
19
Altera PHYLite for Parallel Interfaces IP Core User Guide
Altera Corporation