Maxim Integrated 71M6533-DB - Manual (Page 52)

71M6533- DB Demo Board User’s Manual
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2.5.4 HARDWARE WATCHDOG TIMER
The hardware watchdog timer of the 71M6533 is disabled when the voltage at the V1 pin is at 3.3V (V3P3). On
the Demo Boards, this is done by plugging in a jumper at TP10 between the V1 and V3P3 pins.
Programming the flash memory or emulation using the ADM51 In-Circuit-Emulator can only
be done when a jumper is plugged in at TP10 between V1 and V3P3.
Conversely, removing the jumper at TP10 will enable the hardware watchdog timer.
2.5.5 LCD
Various tests of the LCD interface can be performed with the Demo Board, using the serial command line
interface (CLI):
Setting the LCD_EN register to 1 enables the display outputs.
Register Name Address [bits] R/W Description
LCD_EN 2021[5] R/W Enables the LCD display. When disabled, VLC2, VLC1, and
VLC0 are ground as are the COM and SEG outputs.
To access the LCD_EN register, we apply the following CLI commands:
>RI21$ Reads the hex value of register 0x2021
>25 Response from Demo Code indicating the bit 5 is set
>RI21=5 Writes the hex value 0x05 to register 0x2021 causing the display to be switched off
>RI21=25 Sets the LCD_EN register back to normal
The 71M6533 provides a charge pump capable of boosting the 3.3VDC supply voltage up to 5.0VDC. The
boost circuit is enabled with the LCD_BSTEN register. The 6533 Demo Boards have the boost circuit enabled by
default.
Register Name Address [bits] R/W Description
LCD_BSTEN 2020[7] R/W Enables the LCD voltage boost circuit.
To disable the LCD voltage boost circuit, we apply the following CLI commands:
>RI20$ Reads the hex value of register 0x2020
>8E Response from Demo Code indicating the bit 7 is set
>RI20=E Writes the hex value 0x0E to register 0x2020 causing the LCD boost to be switched off
>RI20=8E Enables the LCD boost circuit
The LCD_CLK register determines the frequency at which the COM pins change states. A slower clock means
lower power consumption, but if the clock is too slow, visible flicker can occur. The default clock frequency for
the 71M6533-DB Demo Boards is 150Hz (LCD_CLK = 01).
Register Name Address [bits] R/W Description
LCD_CLK[1:0] 2021[1:0] R/W Sets the LCD clock frequency, i.e. the frequency at which SEG
and COM pins change states.
f
w
= CKADC/128 = 38,400
00: f
w
/2
9
, 01: f
w
/2
8
, 10: f
w
/2
7
, 11: f
w
/2
6
To change the LCD clock frequency, we apply the following CLI commands:
>RI21$ Reads the hex value of register 0x2021
>25 Response from Demo Code indicating the bit 0 is set and bit 1 is cleared.
>RI21=24 Writes the hex value 0x24 to register 0x2021 clearing bit 0 – LCD flicker is visible now