Kontron KTC5520-EATX - Manual (Page 52)

36 KTC5520/EATX
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5.1.4.1 CPU Configuration sub-menu
Feature Options Description Setup Help
Manufacturer Intel Displays the processor manufacturer name. N/A, display only.
CPU Brand string
Reads and display the 48 bytes CPU Brand
string from the CPU MSR.
N/A, display only.
Frequency X Ghz Displays the current processor core(s) speed. N/A, display only.
BCLK Speed x MHz Displays the surrent BCLK speed N/A, display only.
Cache L1 X KB
Displays amount of Level 1 processor cache per
processor.
N/A, display only.
Cache L2 X KB/MB
Displays amount of Level 2 processor cache per
processor.
N/A, display only.
Cache L3 X KB/MB
Displays amount of Level 3 processor cache per
processor.
N/A, display only.
Ratio Status
Unlocked
Locked
Lock status of the FSB multiplier.
Sets the ratio between
CPU Core Clock and the
FSB Frequency.
Ratio Actual Value x
Displays current processor FSB multiplier value
(FSB time ratio = processor core speed).
N/A, display only.
Processor Power
Management
Configuration
N/A
Press Enter to go to sub screen "Processor
Power Management Configuration".
Configure CPU EIST
and C-state
function.
Ratio CMOS Setting x
Selects the processor FSB ratio value (FSB x
ratio = processor core speed).
Sets the ratio
between CPU Core
Clock and the FSB
Frequency.
Hardware Prefetcher
Disabled
Enabled
The hardware prefetcher looks at streams of
data. The hardware prefetcher assumes that if
a line A and A+1 were requested, then line A+2
also will be requested. The data is prefetched
into L2 from external memory. Disabling of the
hardware prefetcher may impact processor
performance.
Default should be enabled. Optionally for DP/
MP servers, the default may be set based on
performance results observed during platform
validation and testing with standard
workloads.
For UP platforms,
leave it enabled.
For DP/MP servers,
it may use to tune
performance to the
specific application.
Adjacent Cache Line
Prefetch
Disabled
Enabled
When enabled the Adjacent Cache Line
Prefetcher fetches both cache lines that
comprise a cache line pair (128 bytes) when it
determines required data is not currently in its
cache. When the Adjacent Cache Line
Prefetcher is disabled, the processor will only
fetch the cache line (64 bytes) that contains
the data currently required by the processor.
Note: Single processor platforms should
enable it. It is recommended that server
platforms disable it. Optionally for DP/MP
servers, the default may be set based on
performance results observed during platform
validation and testing with standard
workloads.
For UP platforms,
leave it enabled.
For DP/MP servers,
it may use to tune
performance to the
specific application.