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B.2 post code checkpoints – Kontron KTC5520-EATX User Manual

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B-2

KTC5520/EATX

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B.2

POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The
following table describes the type of checkpoints that may occur during the POST portion of the BIOS. All
POST Codes can be seen through the Web Management Interface in section Control.

Checkpoint

Description

03

Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data

area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as

mentioned in the Kernel Variable "wCMOSFlags."

04

Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK.

Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad,

update CMOS with power-on default values and clear passwords. Initialize status register A.
Initializes data variables that are based on CMOS setup questions. Initializes both the 8259

compatible PICs in the system

05

Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.

06

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch

handler. Enable IRQ-0 in PIC for system timer interrupt.
Traps INT1Ch vector to "POSTINT1ChHandlerBlock."

08

Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller

command byte is being done after Auto detection of KB/MS using AMI KB-5.

C0

Early CPU Init Start -- Disable Cache - Init Local APIC

C1

Set up boot strap processor Information

C2

Set up boot strap processor for POST

C5

Enumerate and set up application processors

C6

Re-enable cache for boot strap processor

C7

Early CPU Init Exit

0A

Initializes the 8042 compatible Key Board Controller.

0B

Detects the presence of PS/2 mouse.

0C

Detects the presence of Keyboard in KBC port.

0E

Testing and initialization of different Input Devices. Also, update the Kernel Variables.
Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.

Uncompress all available language, BIOS logo, and Silent logo modules.

13

Early POST initialization of chipset registers.

24

Uncompress and initialize any platform specific BIOS modules.

30

Initialize System Management Interrupt.

2A

Initializes different devices through DIM.
See DIM Code Checkpoints section of document for more information.

2C

Initializes different devices. Detects and initializes the video adapter installed in the

system that have optional ROMs.

2E

Initializes all the output devices.

31

Allocate memory for ADM module and uncompress it. Give control to ADM module for

initialization. Initialize language and font modules for ADM. Activate ADM module.

33

Initializes the silent boot module. Set the window for displaying text information.

37

Displaying sign-on message, CPU information, setup key message, and any OEM specific

information.

38

Initializes different devices through DIM. See DIM Code Checkpoints section of document

for more information.