HID Hi-O iCLASS Installation Guide - Manual (Page 33)

iCLASS OEM75 Integration Guide, 3141-907, Rev. B.0
January 2014 Page 33 of 49
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Host I²C Master Read Function
1. The master CPU issues an I²C bus Start.
2. The master CPU sends the address of the OEM75 with the least significant bit set to one.
This indicates the address is a read address.
3. Read one byte from the OEM75. This is the number of bytes available to read from
theOEM75.
4. Read all available bytes from the OEM75.
5. The master CPU issues an I²C bus Stop.
Peripheral Processor I²C Slave Interrupt Processing:
1. Before any I²C transmission, the OEM75 is in the IDLE state.
2. The first I²C interrupt occurs after a complete transmission of the address byte from the
host. If the first byte is an I²C Write address, the I²C state changes to WRITING, else a read
address is assumed and the state changes to READING.
3. Subsequent reads or writes are processed until the message is transferred.
4. The I²C state machine is reset in hardware when an I²C stop is issued by the master CPU.