HID Hi-O iCLASS Installation Guide - Manual (Page 27)

iCLASS OEM75 Integration Guide, 3141-907, Rev. B.0
January 2014 Page 27 of 49
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6.7 SPI Message Transmission
SPI Write Function is the external host master SPI sends a message to the OEM75 slave SPI. SPI
Read Function is the external host master SPI queries for a message from the OEM75 slave SPI. In
both cases, transferred are two bytes over the SPI to set up a message transfer. The first SPI byte
transmitted indicates write or read. The next byte transferred exchanges a number indicating the
message size in bytes.
6.7.1 Host SPI Master Write Function
1. Assert the Slave Select (SS) for the OEM 75.
2. Send an SPI Write (0x08) command byte to the OEM75, then delay approximately 50
microseconds to allow the OEM75 processor to process an SPI interrupt and determine the
SPI state.
3. Send a byte to the OEM75 indicating the number of bytes in the message about to be sent
and delay approximately 50 microseconds to allow the OEM75 processor to process an
SPI interrupt and store the message size byte.
4. Send all message bytes with a 50 microsecond delay between each byte.
6.7.2 Host SPI Master Read Function
1. Assert the Slave Select (SS) for the OEM 75.
2. Send an SPI Read (0x00) command byte to the OEM75, then delay approximately 50
microseconds to allow the OEM75 processor to process an SPI interrupt and determine the
SPI state.
3. Send a dummy byte (0x00) to the OEM75 to drive a return value from the OEM75
indicating the number of bytes available for transfer.
4. If the returned number of bytes is non-zero, then send that number of dummy bytes to the
OEM 75 and collect all the message data after each transfer. Remember to send all bytes
with a 50 microsecond delay between each byte.
6.7.3 Peripheral Processor SPI Slave Interrupt Processing
1. Before any SPI transmission, the slave SPI is in the IDLE state.
2. The first SPI interrupt occurs after a complete transmission of a byte from the host. If the
first byte is an SPI Write (0x08) byte, the SPI state changes to WAITING FOR MESSAGE
BYTE from the core processor. If it is an SPI Read (0x00) byte, then, the SPI state changes
to MESSAGE BYTE REQUESTED and the number of available bytes is loaded into the
SPI register. Otherwise, a null (0x00) byte is loaded into the SPI register.
3. The next SPI interrupt occurs after a complete transmission of a byte from the core
processor. If the peripheral processor’s SPI state is WAITING FOR MESSAGE BYTE, the
byte just transferred is stored in the circular receive buffer for incoming messages. If the
peripheral processor’s SPI state is MESSAGE BYTE REQUESTED, then the next available
byte is stored in the SPI register.