Watlow CLS200, MLS300 and CAS200 - Manual (Page 31)

Chapter 2: Modbus-RTU Protocol
Communications Specification 25
The data field can be nonexistent (of zero length) in certain kinds of
messages, where the function code alone specifies the action.
Contents of the Error Checking Field
The error checking field contains a 16-bit value implemented as two 8-
bit bytes. The error check value is the result of a Cyclical Redundancy
Check (CRC) calculation performed on the message contents.
The CRC field is appended to the message as the last field in the
message. When this is done, the low-order byte of the field is appended
first, followed by the high-order byte. The CRC high-order byte is the
last byte to be sent in the message.
How Characters are Transmitted Serially
When messages are transmitted on standard Modbus-RTU serial
networks, each character or byte is sent in this order (left to right):
Least Significant Bit (LSB).............Most Significant Bit (MSB)
The bit sequence is:
CRC Error Checking
All messages include an error-checking field that is based on a Cyclical
Redundancy Check (CRC) method. The CRC field checks the contents
of the entire message. It is applied regardless of any parity check
method used for the individual characters of the message.
The CRC field is two bytes, containing a 16-bit binary value. The CRC
value is calculated by the transmitting device, which appends the CRC
to the message. The receiving device recalculates a CRC during receipt
of the message, and compares the calculated value to the actual value it
received in the CRC field. If the two values are not equal, an error
results.
The CRC is started by first preloading a 16-bit register to all 1’s. Then a
process begins of applying successive 8-bit bytes of the message to the
current contents of the register. Only the 8 bits of data in each character
are used for generating the CRC. Start and stop bits do not apply to the
CRC.
During generation of the CRC, each 8-bit character is exclusive ORed
with the register contents. Then the result is shifted in the direction of
the least significant bit (LSB), with a zero filled into the most significant
bit (MSB) position. The LSB is extracted and examined. If the LSB was
a 1, the register is then exclusive ORed with a preset, fixed xA001. If the
LSB was a 0, no exclusive OR takes place.
Start 1 2 3 4 5 6 7 8 Stop Stop