IEI Integration NOVA-945GSE v1.01 - Manual (Page 38)

NOVA-945GSE 5.25” SBC
Page 38
2.5.3 Intel
®
ICH7-M Low Pin Count (LPC) Interface
The ICH7-M LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH7-M is connected to the following components:
BIOS chipset
Super I/O chipset
2.5.4 Intel
®
ICH7-M PCI Interface
The PCI interface on the ICH7-M is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to seven PCI bus masters
The PCI bus is connected to a PC/104-Plus connector as shown in
710H
Figure 2-10.
Figure 2-10: PC/104-Plus Connector