3 mute register, 4 master clock input (mclk), 5 power-off conditions – Rainbow Electronics AT73C246 User Manual
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11050A–PMAAC–07-Apr-10
AT73C246
Figure 12-4. AC / DC Coupled Load Management Schematic View
Figure 12-5. Audio Codec Typical Startup and Shutdown Waveforms With AC Coupled Loads.
12.4.1.3
MUTE Register
By default, the audio codec starts muted. To enable the audio processing, the MUTE register
(0x15) must be cleared. Unmute operation can be performed before or after releasing the
STANDBY mode. During operation, this register provides a convenient way of muting the audio
signal without changing the various gain registers.
12.4.1.4
Master Clock Input (MCLK)
The Audio Controller is clocked by MCLK pin. Therefore a clock must be present at this pin
before each codec control change. Particularly, the master clock must be present at power-on,
power-off, gain change, path change. The master clock must also be available when fully analog
path are used.
12.4.1.5
Power-off Conditions
Three audio codec power-off conditions can occur:
• Sofware request (ENAC = 0 in AUTOSTART register). In this case, the codec is smoothly
powered off by the audio controller.
• PMU Power-off event or Standby event (as defined in
Conditional Transitions” on page 27
). In this case, the codec is smoothly powered off with a
AT73C246
VMID
AGND
AVDD
VDD4
VIN4
LDO4
200k
10uF
200k
ENAC
1uF
HPL
HPR
DCBLOCK.ONHP
LEFT
RIGHT
VMID
BUFFER
S1
S2
C
L
C
R
R
R
R
L
VDD4
VMID
HP(L/R)
DCBLOCK
ENAC
STANDBY
S1 & S2
S1 AND S2 OPENED
BY AUDIO CODEC