Rainbow Electronics AT73C246 - Manual (Page 36)

36
11050A–PMAAC–07-Apr-10
AT73C246
11.5 DCDC0 and DCDC1 Functional Description
DCDC0 and DCDC1 are 2 identical high performance synchronous step-down (buck) convert-
ers. They feature:
• 2 control modes: PFM and PWM,
• A soft start circuit,
• A software programmable output voltage between 0.8 and 3.6V with automatic ramping for
DVS application,
• An Over-Current-Protection circuit,
• A 180 degree out of phase operating mode.
11.5.1 PFM and PWM Control Modes
Pulse Frequency Modulation control is an hysteretic control of the output voltage. It is specially
intended for light loads (< 50mA typ). In this mode, the DCDC converter exhibits a very low qui-
escent current (< 50
µ A) thus achieving very high efficiency at light loads. The frequency of
operation in this mode is not fixed but proportional to the load current.
Pulse Width Modulation control is a fixed frequency, variable duty cycle control of the DCDC
converter. It has a fast and precise feedback loop specially intended to handle hard loads and
low output ripple voltage.
At start-up, DCDC0 and DCDC1 operate in PWM mode. This way, high load at CPU boot are
properly handled. Through software control in registers VDD0_CTRL (0x06) and VDD1_CTRL
(0x07), the user may enter the low-power mode (PFM) when the application consumption is
reduced.
11.5.2 Soft-start Circuit
DCDC0 and DCDC1 feature a soft start circuit to prevent high input current while charging the
output capacitor from 0V to the default output voltage. Typically, the in-rush current at start-up
(with no load) is limited to 30 mA.
11.5.3 Output Voltage Programming
DCDC0 and DCDC1 output voltages can be managed through software control in registers
VDD0_CTRL (0x06) and VDD1_CTRL (0x07). 50mV steps are provided from 0.8V to 3.6V. It is
recommended to use the automatic ramping function in register PMU_SUPPLY_CTRL (0x04) to
achieve smooth operation. When the DVS_VDD
{0,1}
bit is active (default mode), output voltages
are ramped from the current value to the final value in 50mV / 280us steps. For users who intend
to disable the DVS_VDD
{0,1}
bit, a maximum of 4 steps (= 200mV) per 100us is allowed.
At power up, DCDC0 and DCDC1 default output voltages are respectively 1.85V and 1.20V. For
different default output voltages, please contact Atmel.
11.5.4 180 ° Out-of-phase Operation
DCDC0 and DCDC1 can be operated in-phase or at 180 ° out-of-phase according to the selec-
tion bit in register PMU_SUPPLY_CTRL (0x04). When operated in phase both converters will
start charging their inductor at the same time. When operated at 180
° out-of-phase, the inductor
charge start time will be shifted by half a 2MHz clock delay (= 250ns) from one converter to the
other. This latter scheme tends to average the input current of both DCDC converters.