Rainbow Electronics AT73C246 - Manual (Page 58)

58
11050A–PMAAC–07-Apr-10
AT73C246
12.4.1 Audio Codec General Recommendations
12.4.1.1 V
MID
• V
MID
is the common mode voltage of the audio codec analog core. It is recommended to
decouple this voltage with a 1uF capacitor to ensure low noise operation as well as slow
(thus silent) transients at codec power up and power down.
• The V
MID
capacitor is charged and discharged whenever the ENAC bit is set or cleared.
Particularly, placing the audio codec in STANDBY mode does not discharge the V
MID
capacitor. The software WAIT operations in the previous diagram (step #5 and step #8 in
“Audio Codec Typical Control Sequence” on page 57 ) should accommodate V
MID
's settling
time constant. See “Audio Codec Bias” on page 22. .
12.4.1.2 AC / DC Coupled Load Management
• By default the audio codec is in DC-coupled load configuration: DCBLOCK = 0 in register
AUDIO_CONTROL(0x11). In this case, a virtual ground voltage is provided on pin HPVCM (a
buffered version of V
MID
). It allows to directly connect headphones or line loads between
HPVCM and HPL(or R) without any coupling capacitors. To prevent any audio pop at start-up
or shutdown in this DC coupling mode, the audio codec fastly starts HPL, HPR and HPVCM
outputs shorted all together. No software management is required to achieve pop-less
operation.
• If output loads are AC coupled to the headphone amplifier, the audio codec DCBLOCK bit
must be set and unset as described in “Audio Codec Typical Control Sequence” on page 57 .
This bit partially controls the two switches S1 and S2 described in the following figure. When
DCBLOCK = 1 and the headphone amplifier is OFF, the output coupling capacitors are
charged and discharged by the amplifier “VMID_BUFFER”. In order to achieve silent startup
and shutdown, the following rules must be respected:
– DCBLOCK = 0 at supply power-on and power-off. This ensures that the LDO4
power-on and power-off transients are not transmitted to the audio loads.
– DCBLOCK = 1 when ENAC = 1. Particularly, DCBLOCK must be set before
ENAC=1 and unset after ENAC=0. This ensures that the full VMID waveform is
properly buffered to the output loads.
– DCBLOCK = 1 after ENAC = 0 and until V
MID
capacitor is fully discharged. At codec
shutdown (ENAC=0), VMID will discharge slowly. The VMID_BUFFER ensures slow
and silent discharge of the output coupling capacitors, and needs S1 and S2 to be
closed.