Rainbow Electronics ATtiny26L - Manual (Page 73)

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ATtiny26(L)
1477B–AVR–04/02
Start Condition Detector The start condition detector is shown in Figure 44. The SDA line is delayed (in the range
of 50 to 300 ns) to ensure valid sampling of the SCL line.
The start condition detector is working asynchronously and can therefore wake up the
processor from the Power-down sleep mode. However, the protocol used might have
restrictions on the SCL hold time. Therefore, when using this feature in this case the
oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribu-
tion” on page 25) must also be taken into the consideration.
Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative
tasks due to its flexible design.
Half-duplex Asynchronous
Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more
compact and higher performance UART than by software only.
4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note
that if the counter is clocked externally, both clock edges will generate an increment.
12-bit Timer/Counter Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
Edge Triggered External
Interrupt By setting the counter to maximum value (F) it can function as an additional external
interrupt. The overflow flag and interrupt enable bit are then used for the external inter-
rupt. This feature is selected by the USICS1 bit.
Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock
strobe.