Rainbow Electronics ATtiny26L - Manual (Page 118)

118
ATtiny26(L)
1477B–AVR–04/02
Fi gur e 6 5. P a ral l e l P ro g ram m i n g T im in g , L o a di n g S eq u e nc e w i th Tim i n g
Requirements
(1)
Note: 1. The timing requirements shown in Figure 64 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply
to loading operation.
Figure 66. Parallel Programming Timing, Reading Sequence (Within the Same Page)
with Timing Requirements
()
Note: 1. The timing requirements shown in Figure 64 (i.e. t
DVXH
, t
XHXL
, and t
XLDX
) also apply
to reading operation.
XTAL1
PAGEL/BS1
XLXH
t
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) DATA
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XLXH
t
XLXH
t
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) DATA
PAGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE) READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BHDV
t
OLDV
t
XLOL
t OHDZ