Rainbow Electronics ATtiny26L - Manual (Page 36)

36
ATtiny26(L)
1477B–AVR–04/02
Timer/Counter Interrupt Mask
Register – TIMSK
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26/L and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match A, interrupt is enabled. The corresponding interrupt at
vector $003 is executed if a compare match A occurs. The Compare Flag in
Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match B, interrupt is enabled. The corresponding interrupt at
vector $004 is executed if a compare match B occurs. The Compare Flag in
Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26/L and always read as zero.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1)
is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$006) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0)
is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26/L and always reads as zero.
Bit 7 6 5 4 3 2 1 0
$39 ($59) – OCIE1A OCIE1B – – TOIE1 TOIE0 – TIMSK
Read/Write R R/W R/W R R R/W R/W R
Initial Value 0 0 0 0 0 0 0 0