Rainbow Electronics ATtiny26L - Manual (Page 25)

25
ATtiny26(L)
1477B–AVR–04/02
System Clock and
Clock Options
Clock Systems and their
Distribution Figure 26 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 41. The clock systems
are detailed below.
Figure 26. Clock Distribution
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Reg-
ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and USI.
The I/O clock is also used by the External Interrupt module, but note that some external
interrupts are detected by asynchronous logic, allowing such interrupts to be detected
even if the I/O clock is halted.
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-
rate ADC conversion results.
General I/O
modules
Timer/Counter1 ADC CPU Core RAM
clk
I/O AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
clk
FLASH
clk
ADC
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
PLL
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
External RC
Oscillator
clk
PLL
clk
PCK
External clock