Timer/counter1 output compare registerb – ocr1b, Timer/counter1 output compare registerc – ocr1c, Pll control and status register – pllcsr – Rainbow Electronics ATtiny26L User Manual
Page 53: Attiny26(l)
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ATtiny26(L)
1477B–AVR–04/02
ware write that sets TCNT1 and OCR1A to the same value does not generate a
compare match.
A compare match will set the compare interrupt flag OCF1A after a synchronization
delay following the compare event.
Timer/Counter1 Output
Compare RegisterB – OCR1B
The Output Compare Register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously com-
pared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A
compare match does only occur if Timer/Counter1 counts to the OCR1B value. A soft-
ware write that sets TCNT1 and OCR1B to the same value does not generate a
compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization
delay following the compare event.
Timer/Counter1 Output
Compare RegisterC – OCR1C
The Output Compare Register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously com-
pared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts
to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value
does not generate a compare match.
If the CTC1 bit in TCCR1B is set, a compare match will clear TCNT1 and set an Over-
flow Interrupt Flag (TOV1). The flag is set after a synchronization delay following the
compare event.
This register has the same function in normal mode and PWM mode.
PLL Control and Status
Register – PLLCSR
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26/L and always read as zero.
• Bit 2 – PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchro-
nous clock mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1
clock source. If this bit is cleared, the synchronous clock mode is enabled, and system
clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is
set. It is safe to set this bit only when the PLL is locked i.e., the PLOCK bit is 1.
Bit
7
6
5
4
3
2
1
0
$2C ($4C)
MSB
LSB
OCR1B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$2B ($4B)
MSB
LSB
OCR1C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$29 ($29)
–
–
–
–
–
PCKE
PLLE
PLOCK
PLLCSR
Read/Write
R
R
R
R
R
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0/1
0