Status register – sreg, Attiny26(l) – Rainbow Electronics ATtiny26L User Manual

Page 18

ATtiny26(L)

1477B–AVR–04/02

Note:

1. Reserved and unused locations are not shown in the table.

All ATtiny26/L I/O and peripheral registers are placed in the I/O space. The I/O locations
are accessed by the IN and OUT instructions transferring data between the 32 general
purpose working registers and the I/O space. I/O Registers within the address range
$00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these regis-
ters, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set chapter for more details. For compatibility with future
devices, reserved bits should be written zero if accessed. Reserved I/O memory
addresses should never be written.

The I/O and peripheral control registers are explained in the following sections.

Status Register – SREG

The AVR Status Register – SREG – at I/O space location $3F is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in the Interrupt Mask Registers –
GIMSK and TIMSK. If the Global Interrupt Enable Register is cleared (zero), none of the
interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the
SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the
Instruction Set Description for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the Instruction Set Description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set Description for detailed information.

$06($26)

ADCSR

ADC Control and Status Register

$05($25)

ADCH

ADC Data Register High

$04($24)

ADCL

ADC Data Register Low

Table 1. ATtiny26/L I/O Space

(1)

(Continued)

Address Hex

Name

Function

Bit

$3F ($5F)

SREG

Read/Write

R/W

Initial Value