Rainbow Electronics ATtiny26L - Manual (Page 65)

65
ATtiny26(L)
1477B–AVR–04/02
the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written
to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-
wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF flag is set (one) when a stop condition is
detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt
flag. This signal is useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.
The flag is only valid when Two-wire mode is used. This signal is useful when imple-
menting Two-wire bus master arbitration.
• Bits 3..0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be
read or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external
clock edge detector, by a Timer/Counter0 overflow, or by software using USICLK or
USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For
external clock operation a special feature is added that allows the clock to be generated
by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK
bit while setting an external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(SCK/SCL) are can still be used by the counter.
USI Control Register – USICR
The Control Register includes interrupt enable control, wire mode setting, clock select
setting, and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending
interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending inter-
rupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed.
Bit 7 6 5 4 3 2 1 0
$0D ($2D) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0