Rainbow Electronics ATtiny26L - Manual (Page 58)

58
ATtiny26(L)
1477B–AVR–04/02
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1
MHz. This is the typical value at V
CC
= 5V. See characterization data for typical values at
other V
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset
interval can be adjusted from 16 to 2048 ms. The WDR – Watchdog Reset – instruction
resets the Watchdog Timer. Eight different clock cycle periods can be selected to deter-
mine the reset period. If the reset period expires without another Watchdog Reset, the
ATtiny26/L resets and executes from the Reset Vector. For timing details on the Watch-
dog Reset, refer to page 24.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 38. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26/L and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can be cleared only when the
WDCE bit is set(one). To disable an enabled Watchdog Timer, the following procedure
must be followed:
Normally 1 MHz
WATCHDOG
PRESCLALER
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDE
MCU RESET
Bit 7 6 5 4 3 2 1 0
$21 ($41) – – – WDCE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0