Lvdcon – Samsung S3F80JB User Manual
Page 85

CONTROL REGISTERS
S3F80JB
4-18
LVDCON
— LVD Control Register
E0H Set1 Bank1
Bit
Identifier
.7 .6 .5 .4 .3 .2 .1 .0
Reset Value
– – – – – – – 0
Read/Write
– – – – – – –
R/W
Addressing Mode
Register addressing mode only
.7 – .1
Not used for S3F80JB.
.0
LVD Flag (2.3V) Indicator Bit
0
V
DD
≥
LVD_FLAG Level (2.3V)
1
V
DD
< LVD_FLAG Level (2.3V)
NOTE: When LVD detects LVD_FLAG level (2.3V), LVDCON.0 flag bit is set automatically. When VDD is upper 2.3V,
LVDCON.0 flag bit is cleared automatically.