Samsung S3F80JB - Manual (Page 73)

CONTROL REGISTERS S3F80JB
4-6
CACON
— Counter A Control Register F3H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 Counter A Input Clock Selection Bits
0 0 f
OSC
0 1 f
OSC
/2
1 0 f
OSC
/4
1 1 f
OSC
/8
.5 and .4 Counter A Interrupt Timing Selection Bits
0 0 Elapsed time for Low data value
0 1 Elapsed time for High data value
1 0 Elapsed time for combined Low and High data values
1 1 Not used for S3F80JB.
.3 Counter A Interrupt Enable Bit
0 Disable interrupt
1 Enable interrupt
.2 Counter A Start Bit
0 Stop counter A
1 Start counter A
.1 Counter A Mode Selection Bit
0 One-shot mode
1 Repeating mode
.0 Counter A Output Flip-Flop Control Bit
0 Flip-Flop Low level (T-FF = Low)
1 Flip-flop High level (T-FF = High)