Intel – Intel NetStructure MPCBL0001 User Manual
Page 20
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Technical Product Specification
Order #273817
Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Contents
• 16-bits wide, 66 MHz clock, 8x data transfer (octal pumped)
• Supports 64-bit inbound, 32-bit outbound addressing
The MCH I/O subsystems interface incorporates four hub interfaces. Each Hub interface is a point-
to-point connection between the MCH and an I/O bridge/device. The various components of the
chipset communicate via these connected hub interfaces:
•
The first hub link connects the MCH to the ICH3.
•
The next two hub link interfaces connect the MCH to P64H2 components.
•
The remaining hub link is unused.
2.2.2.2
Intel
®
82801CA I/O Controller Hub 3 (U7)
The Intel
®
82801CA I/O Controller Hub 3 (IHC3) provides the legacy I/O subsystem and
integrates advanced I/O functions. ICH3 features are listed below:
•
IDE interface controller
•
Three Universal Host Controller Interface (UHCI)
•
USB host controllers supporting up to 6 ports (MPCBL0001 SBC implementation supports
one port on the front panel)
•
Integrated I/O APIC
•
SMBus 2.0 controller
•
LPC interface
•
Watchdog timer #3 (see
“Watchdog Timers (WDTs)” on page 64
•
PCI 2.2 bus interface supporting 32bit/33 MHz operation
•
Connects to MCH through Hub Interface A (HI 1.5)
The MPCBL0001 SBC implements one USB port and does not use the ICH3 PCI connection.
2.2.2.2.1
PCI Bus Master IDE Interface (J24)
The ICH3 acts as a PCI based, enhanced IDE, 32-bit interface controller for intelligent disk drives
that have disk controller electronics onboard. The SBC includes a single 40-pin (2 x 20) IDE
connector (J24) that supports one master or one slave device. See
drawing for its location. The IDE controller provides support for an internally
mounted 2.5” hard disk. The IDE controller has the following features:
•
PIO and DMA transfer modes
•
Mode 4 timings
•
Supports Ultra ATA33/66/100 synchronous DMA
•
Buffering for PCI/IDE burst transfers
•
Master/slave IDE mode
•
Support for up to two devices (Master/Slave) via a single primary IDE connector
(MPCBL0001 SBC implementation supports one optional physical 2.5" IDE device)
Note:
Incorporating an optional IDE Hard Disk drive may significantly impact the Reliability
Specifications in
Note:
Performance of the IDE interface may be impacted by the DMA mode and type of DMA transfers