Freescale Semiconductor MC68HC908MR32 User Manual

Freescale Semiconductor Hardware

This manual is related to the following products:

MC68HC908MR16

Table of contents

Document Outline

Revision History
List of Chapters
Table of Contents
Chapter 1 General Description
- 1.1 Introduction
- 1.2 Features
- 1.3 MCU Block Diagram
- 1.4 Pin Assignments
Chapter 2 Memory
- 2.1 Introduction
- 2.2 Unimplemented Memory Locations
- 2.3 Reserved Memory Locations
- 2.4 I/O Section
- 2.5 Memory Map
- 2.6 Monitor ROM
- 2.7 Random-Access Memory (RAM)
- 2.8 FLASH Memory (FLASH)
Chapter 3 Analog-to-Digital Converter (ADC)
- 3.1 Introduction
- 3.2 Features
- 3.3 Functional Description
- 3.4 Interrupts
- 3.5 Wait Mode
- 3.6 I/O Signals
- 3.7 I/O Registers
Chapter 4 Clock Generator Module (CGM)
- 4.1 Introduction
- 4.2 Features
- 4.3 Functional Description
- 4.4 I/O Signals
- 4.5 CGM Registers
- 4.6 Interrupts
- 4.7 Wait Mode
- 4.8 Acquisition/Lock Time Specifications
Chapter 5 Configuration Register (CONFIG)
- 5.1 Introduction
- 5.2 Functional Description
- 5.3 Configuration Register
Chapter 6 Computer Operating Properly (COP)
- 6.1 Introduction
- 6.2 Functional Description
- 6.3 I/O Signals
- 6.4 COP Control Register
- 6.5 Interrupts
- 6.6 Monitor Mode
- 6.7 Wait Mode
- 6.8 Stop Mode
Chapter 7 Central Processor Unit (CPU)
- 7.1 Introduction
- 7.2 Features
- 7.3 CPU Registers
- 7.4 Arithmetic/Logic Unit (ALU)
- 7.5 Low-Power Modes
  - 7.5.1 Wait Mode
  - 7.5.2 Stop Mode
- 7.6 CPU During Break Interrupts
- 7.7 Instruction Set Summary
- 7.8 Opcode Map
Chapter 8 External Interrupt (IRQ)
- 8.1 Introduction
- 8.2 Features
- 8.3 Functional Description
- 8.4 IRQ Pin
- 8.5 IRQ Status and Control Register
Chapter 9 Low-Voltage Inhibit (LVI)
- 9.1 Introduction
- 9.2 Features
- 9.3 Functional Description
- 9.4 LVI Status and Control Register
- 9.5 LVI Interrupts
- 9.6 Wait Mode
- 9.7 Stop Mode
Chapter 10 Input/Output (I/O) Ports (PORTS)
- 10.1 Introduction
- 10.2 Port A
  - 10.2.1 Port A Data Register
  - 10.2.2 Data Direction Register A
- 10.3 Port B
  - 10.3.1 Port B Data Register
  - 10.3.2 Data Direction Register B
- 10.4 Port C
  - 10.4.1 Port C Data Register
  - 10.4.2 Data Direction Register C
- 10.5 Port D
- 10.6 Port E
  - 10.6.1 Port E Data Register
  - 10.6.2 Data Direction Register E
- 10.7 Port F
  - 10.7.1 Port F Data Register
  - 10.7.2 Data Direction Register F
Chapter 11 Power-On Reset (POR)
- 11.1 Introduction
- 11.2 Functional Description
Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC)
- 12.1 Introduction
- 12.2 Features
- 12.3 Timebase
  - 12.3.1 Resolution
  - 12.3.2 Prescaler
- 12.4 PWM Generators
  - 12.4.1 Load Operation
  - 12.4.2 PWM Data Overflow and Underflow Conditions
- 12.5 Output Control
- 12.6 Fault Protection
- 12.7 Initialization and the PWMEN Bit
- 12.8 PWM Operation in Wait Mode
- 12.9 Control Logic Block
- 12.10 PWM Glossary
Chapter 13 Serial Communications Interface Module (SCI)
- 13.1 Introduction
- 13.2 Features
- 13.3 Functional Description
- 13.4 Wait Mode
- 13.5 SCI During Break Module Interrupts
- 13.6 I/O Signals
  - 13.6.1 PTF5/TxD (Transmit Data)
  - 13.6.2 PTF4/RxD (Receive Data)
- 13.7 I/O Registers
Chapter 14 System Integration Module (SIM)
- 14.1 Introduction
- 14.2 SIM Bus Clock Control and Generation
- 14.3 Reset and System Initialization
  - 14.3.1 External Pin Reset
  - 14.3.2 Active Resets from Internal Sources
- 14.4 SIM Counter
  - 14.4.1 SIM Counter During Power-On Reset
  - 14.4.2 SIM Counter and Reset States
- 14.5 Exception Control
  - 14.5.1 Interrupts
    - 14.5.1.1 Hardware Interrupts
    - 14.5.1.2 Software Interrupt (SWI) Instruction
  - 14.5.2 Reset
- 14.6 Low-Power Mode
  - 14.6.1 Wait Mode
  - 14.6.2 Stop Mode
- 14.7 SIM Registers
Chapter 15 Serial Peripheral Interface Module (SPI)
- 15.1 Introduction
- 15.2 Features
- 15.3 Pin Name Conventions
- 15.4 Functional Description
  - 15.4.1 Master Mode
  - 15.4.2 Slave Mode
- 15.5 Transmission Formats
- 15.6 Error Conditions
  - 15.6.1 Overflow Error
  - 15.6.2 Mode Fault Error
- 15.7 Interrupts
- 15.8 Resetting the SPI
- 15.9 Queuing Transmission Data
- 15.10 Low-Power Mode
- 15.11 I/O Signals
- 15.12 I/O Registers
Chapter 16 Timer Interface A (TIMA)
- 16.1 Introduction
- 16.2 Features
- 16.3 Functional Description
- 16.4 Interrupts
- 16.5 Wait Mode
- 16.6 I/O Signals
  - 16.6.1 TIMA Clock Pin (PTE3/TCLKA)
  - 16.6.2 TIMA Channel I/O Pins (PTE4/TCH0A-PTE7/TCH3A)
- 16.7 I/O Registers
Chapter 17 Timer Interface B (TIMB)
- 17.1 Introduction
- 17.2 Features
- 17.3 Functional Description
- 17.4 Interrupts
- 17.5 Wait Mode
- 17.6 I/O Signals
  - 17.6.1 TIMB Clock Pin (PTE0/TCLKB)
  - 17.6.2 TIMB Channel I/O Pins (PTE1/TCH0B-PTE2/TCH1B)
- 17.7 I/O Registers
Chapter 18 Development Support
- 18.1 Introduction
- 18.2 Break Module (BRK)
- 18.3 Monitor ROM (MON)
  - 18.3.1 Functional Description
  - 18.3.2 Security
Chapter 19 Electrical Specifications
- 19.1 Introduction
- 19.2 Absolute Maximum Ratings
- 19.3 Functional Operating Range
- 19.4 Thermal Characteristics
- 19.5 DC Electrical Characteristics
- 19.6 FLASH Memory Characteristics
- 19.7 Control Timing
- 19.8 Serial Peripheral Interface Characteristics
- 19.9 TImer Interface Module Characteristics
- 19.10 Clock Generation Module Component Specifications
- 19.11 CGM Operating Conditions
- 19.12 CGM Acquisition/Lock Time Specifications
- 19.13 Analog-to-Digital Converter (ADC) Characteristics
Chapter 20 Ordering Information and Mechanical Specifications
- 20.1 Introduction
- 20.2 Order Numbers
- 20.3 64-Pin Plastic Quad Flat Pack (QFP)
- 20.4 56-Pin Shrink Dual In-Line Package (SDIP)
Appendix A MC68HC908MR16