Freescale Semiconductor MC68HC908MR32 - Manual (Page 210)

Serial Peripheral Interface Module (SPI)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
210 Freescale Semiconductor
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. See
15.12.2 SPI Status and Control Register .
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
15.6.2 Mode Fault Error .) For the state of
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See
Table 15-3 .
15.11.5 V
SS
(Clock Ground)
V
SS
is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To
reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin
of the slave to the V
SS
pin of the master.
15.12 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register, SPCR
• SPI status and control register, SPSCR
• SPI data register, SPDR
15.12.1 SPI Control Register
The SPI control register (SPCR):
• Enables SPI module interrupt requests
• Selects CPU interrupt requests or DMA service requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Table 15-3. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration State of SS Logic
0 X
(1)
1. X = don’t care
X Not enabled General-purpose I/O; SS ignored by SPI
1 0 X Slave Input-only to SPI
1 1 0 Master without MODF General-purpose I/O; SS ignored by SPI
1 1 1 Master with MODF Input-only to SPI