Freescale Semiconductor MC68HC908MR32 User Manual
Page 33
Memory Map
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
33
$003E
SCI Baud Rate Register
(SCBR)
Read:
0
0
SCP1
SCP0
0
SCR2
SCR1
SCR0
Write:
R
R
R
Reset:
0
0
0
0
0
0
0
0
$003F
IRQ Status/Control Register
(ISCR)
Read:
0
0
0
0
IRQF
0
IMASK1
MODE1
Write:
R
R
R
R
ACK1
Reset:
0
0
0
0
0
0
0
0
$0040
ADC Status and Control
Register (ADSCR)
Read:
COCO
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Write:
R
Reset:
0
0
0
1
1
1
1
1
$0041
ADC Data Register High
Right Justified Mode (ADRH)
Read:
0
0
0
0
0
0
AD9
AD8
Write:
R
R
R
R
R
R
R
R
Reset:
Unaffected by reset
$0042
ADC Data Register Low
Right Justified Mode (ADRL)
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
R
R
R
R
R
R
R
R
Reset:
Unaffected by reset
$0043
ADC Clock Register
(ADCLK)
Read:
ADIV2
ADIV1
ADIV0
ADICLK
MODE1
MODE0
0
0
Write:
R
Reset:
0
0
0
0
0
1
0
0
$0044
SPI Control Register
(SPCR)
Read:
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
Write:
Reset:
0
0
1
0
1
0
0
0
$0045
SPI Status and Control
Register (SPSCR)
Read:
SPRF
ERRIE
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
Write:
R
R
R
R
Reset:
0
0
0
0
1
0
0
0
$0046
SPI Data Register
(SPDR)
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
$0047
↓
$0050
Unimplemented
$0051
TIMB Status/Control Register
(TBSC)
Read:
TOF
TOIE
TSTOP
0
0
PS2
PS1
PS0
Write:
0
TRST
R
Reset:
0
0
1
0
0
0
0
0
$0052
TIMB Counter Register High
(TBCNTH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
U = Unaffected
X = Indeterminate
R
= Reserved
Bold
= Buffered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8)