Figure 2-2, Reserved, 005f, shown in – Freescale Semiconductor MC68HC908MR32 User Manual
Page 28

Memory
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
28
Freescale Semiconductor
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0000
Port A Data Register
(PTA)
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Write:
Reset:
Unaffected by reset
$0001
Port B Data Register
(PTB)
Read:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Write:
Reset:
Unaffected by reset
$0002
Port C Data Register
(PTC)
Read:
0
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Write:
R
Reset:
Unaffected by reset
$0003
Port D Data Register
(PTD)
Read:
0
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Write:
R
R
R
R
R
R
R
R
Reset:
Unaffected by reset
$0004
Data Direction Register A
(DDRA)
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
0
0
0
0
0
0
0
0
$0005
Data Direction Register B
(DDRB)
Read:
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
0
0
0
0
0
0
0
0
$0006
Data Direction Register C
(DDRC)
Read:
0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
Write:
R
Reset:
0
0
0
0
0
0
0
0
$0007
Unimplemented
$0008
Port E Data Register
(PTE)
Read:
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Write:
Reset:
Unaffected by reset
$0009
Port F Data Register
(PTF)
Read:
0
0
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
Write:
R
R
Reset:
Unaffected by reset
$000A
Unimplemented
$000B
Unimplemented
$000C
Data Direction Register E
(DDRE)
Read:
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
Write:
Reset:
0
0
0
0
0
0
0
0
$000D
Data Direction Register F
(DDRF)
Read:
0
0
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
Write:
R
R
Reset:
0
0
0
0
0
0
U = Unaffected
X = Indeterminate
R
= Reserved
Bold
= Buffered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 8)