Figure 4-1. cgm block diagram, Figure 4-2. cgm i/o register summary – Freescale Semiconductor MC68HC908MR32 User Manual
Page 58
Clock Generator Module (CGM)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
58
Freescale Semiconductor
Figure 4-1. CGM Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$005C
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON
BCS
1
1
1
1
Write:
R
R
R
R
R
Reset:
0
0
1
0
1
1
1
1
$005D
PLL Bandwidth Control Register
(PBWC)
Read:
AUTO
LOCK
ACQ
XLD
0
0
0
0
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
$005E
PLL Programming Register
(PPG)
Read:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Write:
Reset:
0
1
1
0
0
1
1
0
R
= Reserved
Figure 4-2. CGM I/O Register Summary
BCS
PHASE
DETECTOR
LOOP
FILTER
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
BANDWIDTH
CONTROL
LOCK
DETECTOR
CLOCK
CGMXCLK
CGMOUT
CGMVDV
CGMVCLK
SIMOSCEN
CRYSTAL OSCILLATOR
INTERRUPT
CONTROL
CGMINT
CGMRDV
PLL ANALOG
÷ 2
CGMRCLK
SELECT
CIRCUIT
LOCK
AUTO
ACQ
VRS[7:4]
PLLIE
PLLF
MUL[7:4]
CGMXFC
V
SS
V
DDA
OSC1
OSC2
TO SIM
TO SIM
PTC2
MONITOR MODE
A
B S*
USER MODE
*WHEN S = 1, CGMOUT = B