Freescale Semiconductor MC68HC908MR32 - Manual (Page 64)

Clock Generator Module (CGM)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
64 Freescale Semiconductor
Figure 4-3 also shows the external components for the PLL:
• Bypass capacitor, C
BYP
• Filter capacitor, C
F
NOTE
Routing should be done with great care to minimize signal cross talk and
noise. (See
4.8 Acquisition/Lock Time Specifications for routing information
and more information on the filter capacitor’s value and its effects on PLL
performance.)
4.4 I/O Signals
This section describes the CGM input/output (I/O) signals.
4.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
4.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
4.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is
connected to this pin.
NOTE
To prevent noise problems, C
F
should be placed as close to the CGMXFC
pin as possible, with minimum routing distances and no routing of other
signals across the C
F
connection.
4.4.4 PLL Analog Power Pin (V
DDA
)
V
DDA
is a power pin used by the analog portions of the PLL. Connect the V
DDA
pin to the same voltage
potential as the V
DD
pin.
NOTE
Route V
DDA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
4.4.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and
PLL.