ProSoft Technology MVI69-101S - Manual (Page 74)

MVI69-101S ♦ CompactLogix or MicroLogix Platform Reference
IEC 60870-5-101 Slave Communication Module
Page 74 of 149 ProSoft Technology, Inc.
March 16, 2009
5.1.1 General Specifications
Single Slot - 1769 backplane compatible
The module is recognized as an Input/Output module and has access to
processor memory for data transfer between processor and module
Ladder Logic is used for data transfer between module and processor.
Sample ladder file included.
Configuration data obtained from configuration text file downloaded to
module. Sample configuration file included.
Supports all CompactLogix processors: L20/L23/L30/L31/L32/L35, L43 and
L45 (L43 and L45 supported with RSLogix 5000 v16.03 or later)
Also supports MicroLogix 1500 LRP
5.1.2 Hardware Specifications
Specification Description
Dimensions Standard 1769 Single-slot module
Current Load 800 mA max@ 5 VDC
Power supply distance rating of 2 (L43 and L45
installations on first 2 slots of 1769 bus)
Operating Temp. 0 to 60°C (32 to 140°F)
Storage Temp. -40 to 85°C (-40 to 185°F)
Relative Humidity 5% to 95% (non-condensing)
LED Indicators Battery and Module Status
Application Status
Serial Port Activity
CFG Port Activity
CFG Port (CFG) RJ45 (DB-9F with supplied cable)
RS-232 only
No hardware handshaking
App Ports (P1,P2) (Serial modules) RS-232, RS-485 or RS-422 (jumper selectable)
RJ45 (DB-9F with supplied cable)
RS-232 handshaking configurable
500V Optical isolation from backplane
Shipped with Unit RJ45 to DB-9M cables for each port
6-foot RS-232 configuration Cable
5.1.3 Functional Specifications
The MVI69-101S module accepts commands from an attached master unit. A
port configured as a virtual slave permits a remote master to interact with all data
contained in the module. This data can be derived from the CompactLogix
processor. The remote master device uses the fully-configured databases in the
module to control outputs and monitor inputs. The module can operate in
balanced or unbalanced mode.
Supports time stamp events
Supports time and data synchronization from a master or the processor