Verilink AS2000: The Basics (880-502981-001) Product Manual - Manual (Page 76)

Monitoring and Troubleshooting
5-10 Verilink Access System 2000: The Basics
the network, depending on the current application module
configuration settings. The ELB can be activated locally, or at the
far end by a command message on the T1 ESF or E1 data link.
Data Port
Loopback (DPLB)
In integrated CSU/DSU modules or standalone DSUs, this
bidirectional loopback returns the data back to the data equipment
and returns the carrier channel signal back to the far end.
Therefore, the DPLB tests the data port cable, the CSU, and the
carrier channel in both directions.
Test Patterns AS2000 application modules have several built-in test patterns.
These test patterns are defined in
Table 5-4 .
Table 5-4 Test Patterns
Option Definition
None This option indicates that no test pattern will be used.
3 in 24 Use 3-in-24 Ones test pattern which consists of three pulses in every 24-bit sequence
(10001000 10000000 00000000). This stress test is useful for testing circuits under
extremely low density conditions. This is mostly useful for T1 AMI.
QRSS Use Quasi-Random Signal Sequence that limits the signal to a maximum of 15 zeros that
can be transmitted sequentially. These signals contain a medley of 20-bit words (except
for more than 15 consecutive 0s). It repeats every 1,048,575 bits. Also, it contains high
density sequences and low density sequences, and sequences that change from low
density to high density and vice versa.
2
20
-1 This pattern tests circuits for equalization and timing. It is the same as QRSS, but without
the 15 zeros restriction.
1/8 This pattern tests the ability of a circuit to support a pattern having the minimum ones
density (containing 7 zeros indicating empty pulses and 1 pulse-1000000). It helps
discover a timing recovery problem. This is mostly useful for T1 AMI.
2
15
-1 This pattern tests circuits for equalization and timing using an alternate pattern for jitter
testing. The pattern repeats every 32,757 bits.
All 0s This pattern is composed entirely of framed zeros (00000000).
All 1s This pattern is comprised entirely of framed ones (11111111). It stresses circuits by
maximizing power consumption.