Verilink AS2000: The Basics (880-502981-001) Product Manual - Manual (Page 29)

System Information
Verilink Access System 2000: The Basics 2-13
Tail Circuit Timing When two synchronous circuits are connected directly to each
other through a crossover connection, they must use a common
clock. In a network duet, one circuit must pass clock to the other.
The circuit which receives timing from another circuit is known as
a tail circuit.
Figure 2-9 illustrates tail-circuit timing. The digital
and cross-connect switch in the main circuit provides clock for the
network in this example.
Figure 2-9 Tail Circuit Timing, Net 1 Source
TABS-Based
Timing Options
The TABS-based modules simply require the user to set the timing
source for each network and data port. If the selected timing
source fails for any reason, the module will automatically use its
internal clock as a backup until the primary source becomes
available again.
ACP-Based
Timing Options
In ACP or mixed ACP/TABS nodes, there are several timing
considerations:
• shelf vs. card timing
• timing source
• shelf sync master
Shelf vs. Card
Timing
For each ACP module, the timing source can be derived from the
shelf timing table or one of its own ports. In either case, two
backup timing sources are available for each module. If one timing
source fails, the module will automatically select the secondary
and, if necessary, then the tertiary (third) timing source.
Shelf timing provides a way for some or all of the modules within a
shelf to use the same clock timing source. It is required for all
modules exchanging data across the shelf midplane.
DSU CSU
Node #1 Node #2 Node #3
Main
Circuit
Crossover Connection
Tail
Circuit
DSU CSU
DSU DSU CSU CSU
Timing
Source
NET
Timing
Source
NET
Timing
Source
NET
Timing
Source
DIU
Timing
Source
CSU
Timing
Source
CSU
Timing
Source
CSU
Timing
Source
P1