Verilink AS2000: The Basics (880-502981-001) Product Manual - Manual (Page 167)

Acronyms and Definitions
Verilink Access System 2000: Basics Glossary-47
terminal timing (TT) DSU clocking option which selects
an external timing input as the
source for the clock used to
control sampling of transmit data.
tertiary synchronization The second alternate source for
clock synchronization of the node.
Can be internal or external. See
primary synchronization and
secondary synchronization .
test mode (TM) An output from DTE in many
synchronous serial interface types
used to indicate that the DCE is in
a test mode.
time division multiplexing Interleaving digital data from
multiple users onto one serial
communication link in a network
line by partitioning line capacity
into time slices or timeslot (TS) .
timeslot (TS) Also called a channel or DS0. A
repeating “slice” of time during
which a certain amount of data is
conveyed between communication
devices. Each timeslot contains 8
bits. Since 8000 timeslots (each a
voice or data sample) are
transmitted per second, the bit
rate for a timeslot is 64 kbit/s.
timing interface unit (TIU) The TIU 2850 module that receives
a timing signal and then makes
that signal available to all other
cards on a shelf using bus C—
rendering bus C unavailable for
any other use. For Telemetry
Asynchronous Block Serial
(TABS) -based modules only.
timing master The module or device providing
clock (timing signals) for a shelf.
transmit data Information leaving the local site
and sent to the network.
TS16 multiframe alignment signal (MAS) Specific to E1 systems, this signal
is a series of four zeros that
occupies positions one to four of
TS16 in frame zero of the channel-
associated signaling multiframe.
TTL Transistor to transistor logic.
twisted pair A pair of insulated conductors that
are twisted around each other,
mainly to reduce the effects of
electrical noise. Twisted pair is
typical of standard telephone
network wiring.