Dac chcd register d 0x4d, Dac chcd register e 0x4e – Sundance SMT943 User Manual
Page 49

User Manual SMT943
Page 49 of 54
Last Edited: 23/08/2011 17:24:00
1
‘1’
DACA in sleep mode.
Setting
Bit 13
Description sleepb
0
‘0’
DACB not in sleep mode.
1
‘1’
DACB in sleep mode.
Setting
Bit 15
Description io_1p8_3p3
0
‘0’
3.3V tolerate pads
1
‘1’
1.8V tolerate pads
DAC chcd Register D 0x4D.
DAC chcd Register D 0x4D
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Reserved
Default
‘00000000’
0
Coarse_daca
Coarse_dacb
Default
‘1111’
‘1111
DAC chcd Register D 0x4D
Setting
Bit 3:0
Description Coarse_dacb
0
DACB Output current scale.
Setting
Bit 7:4
Description Coarse_daca
0
DACA Output current scale.
DAC chcd Register D 0x4D.
DAC chcd Register D 0x4D
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Reserved
Default
‘00000000’
0
Coarse_daca
Coarse_dacb
Default
‘1111’
‘1111
DAC chcd Register D 0x4D
Setting
Bit 3:0
Description Coarse_dacb
0
DACB Output current scale.
Setting
Bit 7:4
Description Coarse_daca
0
DACA Output current scale.
DAC chcd Register E 0x4E.