Sundance SMT943 - Manual (Page 28)

User Manual SMT943 Page 28 of 54 Last Edited: 23/08/2011 17:24:00
CLOCK Register C 0x1C.
Clock Register C 0x1C
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit
3
Bit 2 Bit 1 Bit 0
1 Reserved DET_STAR
T_BYPASS
FB_START
_BYPASS
Default ‘000000’ ‘0’ ‘0’
0 DIV2_DIS DIV_SEL Reserve
d
FB_FD_DESEL Reserved
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0110’
Reset Register C 0x1C
Setting Bit 4 Description FB_FD_DESEL
0 ‘0’ Feedback frequency detector is connected to the lock detector
1 ‘1’ Feedback frequency detector is disconnected from the lock detector
Setting Bit 6 Description DIV_SEL
0 ‘0’ FB Clock divided by 1
1 ‘1’ FB Clock divided by 2
Setting Bit 7 Description DIV2_DIS
0 ‘0’ Normal mode of operation
1 ‘1’ FB Div2 in reset
Setting Bit 8 Description FB_START_BYPASS
0 ‘0’ Normal mode of operation
1 ‘1’ FB Divider can be started with external REF_SEL (pin)
Setting Bit 9 Description DET_START_BYPASS
0 ‘0’ Normal mode of operation
1 ‘1’ FB Divider can be started with external NRESET (pin)
CLOCK Register D 0x1D.
Clock Register D 0x1D
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Reserved
Default ‘01101000’
0 Reserved
Default ‘00000000’