Sundance SMT943 - Manual (Page 47)

User Manual SMT943 Page 47 of 54 Last Edited: 23/08/2011 17:24:00
Default ‘00000’ ‘000’
DAC chcd Register 9 0x49
Setting Bit 7:3 Description QMC offset b[12:8]
0 0
Setting Bit 15:8 Description Ser_dac_data[7:0]
0 0
DAC chcd Register A 0x4A.
DAC chcd Register A 0x4A
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Nco_sel Nco_reg_sel Qmcorr_reg_sel Qmoffset_reg_sel
Default ‘00’ ‘01’ ‘01’ ‘01’
0 Ser_dac_data[15:8]
Default ‘00000000’
DAC chcd Register A 0x4A
Setting Bit 7:0 Description Ser_dac_data[7:0]
0 0
Setting Bit 9:8 Description qmoffset_reg_sel selects sync for loading the QM offset register
0 ‘00’ TXENABLE from FIFO output
0 ‘01’ SYNC from FIFO output
1 ‘10’ Sync_sif_sig
1 ‘11’ Always 0
Setting Bit 11:10 Description qmcorr_reg_sel selects sync for loading the QM correction register
0 ‘00’ TXENABLE from FIFO output
0 ‘01’ SYNC from FIFO output
1 ‘10’ Sync_sif_sig
1 ‘11’ Always 0
Setting Bit 13:12 Description nco_reg_sel selects sync for loading the NCO register
0 ‘00’ TXENABLE from FIFO output
0 ‘01’ SYNC from FIFO output
1 ‘10’ Sync_sif_sig
1 ‘11’ Always 0
Setting Bit 15:14 Description nco_sel selects sync for loading the NCO accumulator
0 ‘00’ TXENABLE from FIFO output
0 ‘01’ SYNC from FIFO output
1 ‘10’ Sync_sif_sig
1 ‘11’ Always 0